System Verilog let construct

Let construct

Very rarely known/used construct, but very helpful.

What it is?

A let declaration defines a template expression (a let body), customized by its ports. A let construct may be instantiated in other expressions.

It is basically a text macro. Just like the `define macro(compiler directive), but bit different than it. Difference between `define and let is that “let” is having local scope where as “`define” is having global scope.

So let macro can have different definition par task/function/module, whereas there could only one `define based macro.

How to use it?

Syntax:

  let (actual/formal variable)=(expression containing actual/formal variables);

Usage example1(Formal variable passed in declaration):

module my_mod(input I, input j);

……

…..

//Definition

let maxab(a,b)=(a>b?a:b);

//Usage

C=maxab(d,e);

…….

…….

endmodule

Usage example2(let construct in assertion):

module m;

logic clk, a, b;

logic p, q, r;

// let with formal arguments and default value on y

let eq(x, y) = x == y;

// without parameters, binds to a, b above

let tmp = a && b;

...

a1: assert property (@(posedge clk) eq(p,q));

always_comb begin

a2: assert (eq(r,s));

a3: assert (tmp);

end

endmodule : m

Usage example3(No formal variable passed in declaration):

module m;

logic clk, a, b;

logic p, q, r;

// let with formal arguments and default value on y

let eq(x, y=b) = x == y;

// without parameters, binds to a, b above

let tmp = a && b;

...

a1: assert property (@(posedge clk) eq(p,q));

always_comb begin

a2: assert (eq(r));

a3: assert (tmp);

end

endmodule : m

In cases where formal variables are not passed remaining variables are assigned value from local scope, in above example value of y is picked from local variable ‘b’.

Where it can be defined:

A let may be declared in any of the following:

— A module

— An interface

— A program

— A checker

— A clocking block

— A package

— A compilation-unit scope

— A generate block

— A sequential or parallel block

— A subroutine