SFI-S(Scalable SerDes Framer Interface)

Introduction

This interface communicates between optical module containing SerDes(Serailizer-Deserializer) and FEC processor and Framer.

Input to optical module is optical signal which need to be converted into electrical signal for processing by OTN Framer. Same way output from framer is converted to optical signal and sent over fiber.

Output of optical receiver is converted to serial bit stream and this serial data is converted to parallel (Deserial) data by SerDes sent to framer for further processing. Similarly parallel data from framer is converted to serial data by SerDes and sent to optical transmitter.

SFIs interface communicates between SerDes and Framer/FEC block.

General characteristics:

1. Point-to-point connections applicable for connection of the Serdes component to the FEC processor, the FEC processor to the Framer or the Serdes component directly to the Framer.

2. n-bit wide (n = 4 to 20) data bus with each channel operating at CEI defined data rates. The Deskew method can be scaled to future CEI- 28 SR speeds.

3. Deskew Channel included in both RX and TX directions contain out of band data samples to enable Deskew algorithm. Deskew Channel is one additional data channel (n + 1), running continuously at full data rate. Deskew algorithm will be operating continuously to monitor skew tracking.

4. By using an alternating odd/even parity frame format on the deskew channel a minimum toggling rate of 1 every 18 bits is guaranteed. This can be used to recover the SFI-S receive clock on the deskew channel only and use DLLs instead of CDRs on the data channels.

5. Minimize power consumption and the number of I/O signals to simplify PC board manufacturing.

6. Maximize commonality of receive and transmit directions and of instantiations in different applications of the bus.

Signal definition:-

Receive path have following signals

Signal name	Direction	Function
RXDATA[n-1:0]	Optics to system	These are n data lanes, which will collect data from optics.
RXDSC	Optics to system	Receive Deskew Channel provides way to measure the skew in each data lanes and align all channels.
RXREFCLK	Optics to system	The Receive Reference Clock (RXREFCK) signal provides reference timing to the Receive interface. RXREFCK is nominally a 50% duty cycle clock with a frequency that is 1/16th of the data bit rate of RXDATA and RXDSC.
RXS	Optics to system	The Receive Status (RXS) signal carries status from the Serdes component to the FEC processor, from the FEC processor to the Framer, or from the Serdes component directly to the Framer. The encoding of RXS is: RXS = ‘b0: Idle, RXS = ‘b1: Receive alarm, Receive alarm shall indicate that RXDATA is not derived from the optical receive signal.

Transmit path have following signals

Signal name	Direction	Function
TXDATA[n-1:0]	System to optics	These are n data lanes, which will be driven to optics.
TXDSC	System to optics	Transmit Deskew Channel provides way to measure the skew in each data lanes and align all channels at the receiver end.
TXREFCLK	System to optics	The Transmit Reference Clock (TXREFCK) signal provides reference timing to the Transmit interface. TXREFCK is nominally a 50% duty cycle clock with a frequency that is 1/16th of the data bit rate of TXDATA and TXDSC.

So from above signals list it is clear that TX/RXDATA carries data to/from FEC/FRAMER block. Apart from data lanes there exists one deskew lane. This lane is used for removing skews from data lanes and aligning them at receiver end.

Complete OTN frame will be carried over DATA lanes. Each data lane is serial lane. Number of data lane in SFIs is configurable from n=4 to 20.

OTN frame stripping:-

OTN frame is distributed across the data lanes in round robin fashion. Very fist bit of OTN frame will be put on the MSB data lane, next bit will be placed on next most data lane likewise, when LSB data lane is reached frame data adding is again started from MSB data lanes.

Following example shows how OTN frame will be distributed for 4 data lane for a byte, the same can be extended for complete frame.(Here it is assumed that SERDES input/output width is 1 bit)

Data lane 3	D.0	D.4
Data lane 2	D.1	D.5
Data lane 1	D.2	D.6
Data lane 0	D.3	D.7

Deskew lane requirement:-

SFIs is a serial protocol, all lanes are working independently. Generally there will be some skew added between all data lanes(most of the time introduce by SerDes).

So if we collect the data from lane with skew in them we will never collect correct OTN frame.Very first thing which should be done before collecting data from the lanes is to remove skew which is present between data lanes.

This is achieved via deskew lane. Deskew lane work as a reference lane skew in each lane is compared against this lane. Deskew lane is formed from the data lanes. It carries reference frame generated by clubbing data bits from data lanes (starting from highest lane to lowest lanes).

Deskew Reference Frame generation:

Deskew reference frame is generated using with Even Parity elements and Odd Parity elements. Each of these parity elements consist of four samples from data lanes followed by even parity of the sample in even parity element and odd parity in odd parity element. So each of parity elements is made of 5 bits (4bit of data bits + 1 parity bit)

Even Parity Element

D0

D1

D2

D3

Even Parity

Odd Parity Element

D0

D1

D2

D3

Odd Parity

To improve number of transition in serial data, data in odd parity elements can be optionally inverted.

Following rules are applied to build Reference Frame

1) Each reference frame always start with even parity pattern.

2) Each reference frame always end with odd parity pattern.

3) Number required parity elements is calculated as shown below

    Number of ref. parity elements= Number of data lanes/number of data samples(4).

SFIs supports 4 to 20 data lanes, so possible size of Deskew lane is as given below

No of lanes	No of ref. parity elements	Deskew frame
4-8	2	EP-->OP
9-12	3	EP-->EP-->OP
13-16	4	EP-->EP-->OP-->OP
17-20	5	EP-->EP-->OP-->EP-->OP

Table-1 Deskew frame as per number of lanes. (EP(Even Parity element) OP(Odd Parity element))

4) For Deskew frame with more than 2 reference parity elements frame start will be marked by two even parity elements.

5) Reference parity element will be generated by filling up highest lane data.

Deskew lane generation example for 4 data lanes

Data lane 3	D3.0	D3.1	D3.2	D3.3	D3.4	D3.5	D3.6	D3.7	D3.8	D3.9
Data lane 2	D2.0	D2.1	D2.2	D2.3	D2.4	D2.5	D2.6	D2.7	D2.8	D2.9
Data lane 1	D1.0	D1.1	D1.2	D1.3	D1.4	D1.5	D1.6	D1.7	D1.8	D1.9
Data lane 0	D0.0	D0.1	D0.2	D0.3	D0.4	D0.5	D0.6	D0.7	D0.8	D0.9
Deskew lane	D3.0	D2.1	D1.2	D0.3	Even parity	D3.5	D2.6	D1.7	D0.8	Even parity

As show in above diagram deskew lane is generated via clubbing data from each data lane sample. Deskew frame generation always start with data lanes with the highest lane which is data lane 3 in this case.  Samples from each subsequent lanes will be put in deskew lane till data sample count is reached to 4 then parity bit is added (even or odd as suggested in Table-1).

Once sample from last lane is put in deskew lane, sample from the highest lanes will be filled till the current reference frame is complete. After than once again samples will be filled from the highest lane.